FLASH memory is generally used on a digital media storage product such as Secure Digital (SD), USB drive, Compact FLASH (CF), MultiMediaCard (MMC), Memory Stick (MS), Smart Media (SM) and others. A FLASH memory controller interfaces with various FLASH memory chips to construct one of the above mentioned digital media storage products. Conventional FLASH memory chips include an 8-bit data bus. A 16 bit FLASH memory chip has the same footprint as that of 8 bit FLASH memory chip. The 16 bit FLASH memory chips usually have the same pin assignment on electrical signals such as chip enable, ready, and control bus. However, the pin assignment for the data bus is generally very different between 8-bit and 16-bit FLASH memory. A conventional 16-bit FLASH memory controller is designed to interface with both 8-bit and 16-bit FLASH memory chips. The FLASH memory configuration on a digital media storage has the following four modes:
1. Single 8-bit access
2. Dual 8-bit parallel access
3. Single 16-bit access
4. Dual 16-bit interleave access
Mode 4, dual 16-bit interleave access, has the best performance, while Mode 1, single 8-bit access, has the lowest performance. Mode 3, single 16-bit access, and mode 2, dual 8-bit parallel access, have a performance rating in between.
Due to data bus pin-out difference between 8-bit and 16-bit flash memory chips, conventionally it requires two different printed circuit boards (PCB) to support the four modes above.
One possible mapping of pins 10 between 8-bit and 16-bit FLASH memory chip is shown in FIG. 1. AHD0 through AHD15 are 16 bits data bus pins of 16-bit FLASH memory chip 12. AD0 through AD7 are 8 bits data bus pins of 8-bit FLASH memory chip 14. NC26, NC27, NC28, NC33, NC40, NC45, NC46, and NC47 are 8 non-connect pins of 8-bit FLASH memory chip 14 mapping to 16-bit FLASH memory chip 12. The term CS- refers to Chip Select, and the term BUSY- refers to Chip Busy. Other FLASH control bus pins are also included.
The conventional FLASH memory chip 14 has an 8-bit data bus (AD) along with chip select (CS-), busy (BUSY-) and other control signals. A 16-bit FLASH memory chip 12 may reside in the same package as that of an 8-bit FLASH memory chip. These two kinds of FLASH memory chips 12 and 14 have the same pin designation for chip select (CS-), busy (BUSY-) and other control signals, except for data bus signals (AD & AHD). One of pin mapping examples 10 of 8-bit FLASH memory chip 14 and 16-bit FLASH memory chip 12 is shown in FIG. 1. Note that data bus pins (AD0-AD7) of 8-bit flash memory 14 are not mapped one-to-one to the lower eight bits data bus (AHD0-AHD7) of 16-bit FLASH memory chip 12. In fact, AD0 through AD7 are mapped to AHD9, 2, 10, 3, 12, 5, 13 and 6 respectively. AHD8, 0, 1, 11, 4, 7, 14 and 15 of 16-bit FLASH memory chip are mapped to the no-connect (NC) pins of 8-bit counter part.
A 16-bit micro-controller (not shown) interfaces through its read/write control signals and data bus UD to a 16-bit FLASH Control Logic with FLASH data bus FD. The FD bus in turn interfaces with one or more 8-bit or 16-bit FLASH memory chips. Due to pin-out difference between 8-bit and 16-bit FLASH memory chip, conventionally it requires two different circuitries or printed circuit boards (PCBs) for these two different kinds of FLASH memory.
FIG. 2 is a block diagram of a circuit 100 for a conventional 16-bit FLASH memory controller 102 to support a single 8-bit access (Access mode 1) 108a or two 8-bit parallel access (Access mode 2) flash memory chips 108a and 108b. 
As in FIG. 1, a FLASH memory controller 102 includes a micro controller 104, host interface 110, a ROM 122, a RAM 124, an internal data bus (UD0-UD15) 112, read/write control 114 and FLASH Control Logic 116. FLASH Control Logic 116 includes an internal data bus (UD0-UD15) 112, a FLASH chip select (FCS0-FCS3), a FLASH control bus (Fcontrol Bus) 118, a FLASH status bus (FBUSY0-FBUSY3) and a FLASH data bus (FD0-FD15).
In the case of single 8-bit access, data bus FD8 through FD15 120 is not connected. In the case of two 8-bit parallel access, control buses are connected together to the FLASH memory controller 102. Two 8-bit parallel access mode generally runs twice as fast as single 8-bit access mode because the access bandwidth is twice the size.
FIG. 3 is a diagram for a conventional 16-bit FLASH memory controller 202 to support a single 16-bit access 208a or two 16-bit interleave access FLASH memory chips 208a and 208b. 16-bit access generates the same performance as that of two 8-bit parallel access, while 16-bit interleave access has the best performance among the four access modes.
In order to have the same 16-bit FLASH memory controller support all four modes of access on the same printed circuit board (PCB), a different routing is required from the high order flash memory controller data bus FD8 through FD15 220 to 8-bit and 16-bit FLASH memory chips 208a and 208b, as shown in FIG. 2 and FIG. 3. Referring now to FIG. 4, conventionally the routing and mapping is done by adding four sets of resistor networks RA, RHA, RB and RHB between FLASH memory controller and 8/16-bit flash memory chips, as shown in FIG. 4.
FIG. 4 is a diagram of a circuit 300 for a conventional 16-bit FLASH memory controller 302 to support a single 8-bit access 308a or two 8-bit parallel access 308a and 308b or a single 16-bit access 308a or two 16-bit interleave access FLASH memory chips 308a and 308b on the same PCB. Four sets of resistor networks 310a-310b, and 312a-312b are utilized to select different modes of operation. Table 1 shows the four possible combinations:
TABLE 1AccessResistor NetworkModeDescriptionRARHARBRHB1Single 8-bit accessInstalled2Dual 8-bit parallel accessInstalledInstalled3Single 16-bit accessInstalled4Dual 16-bit interleave accessInstalledInstalled
One of the possible mappings of pin-outs is shown below:
TABLE 2FLASHmemory8-bit16-bit8 bitMap-16-bitcon-FLASHFLASHMappedFLASHFLASHFLASHFLASHpedFLASHFLASHtrollerResistorChip AChip AtoResistorChip AChip AResistorChip BChip BtoResistorChip BChip BFDNetworkPinoutADAHDNetworkPinoutAHDNetworkPinoutBDBHDNetworkPinoutBHD0RA02909RHA0260RHB02601RA13012RHA1281RHB12812RA231210RHA2302RHB23023Wired3233Wired323RHB33234RA441412RHA4404RHB44045Wired4255Wired425RHB54256RA643613RHA6446RHB64467RA74476RHA7467RHB74678Wired278RB82909RHB82789RHA9299RB93012RHB929910RHA103110wired31210wired311011Wired3311RB113233RHB11331112RHA124112wired41412wired411213RHA134313RB134255RHB13431314Wired4514RB1443613RHB14451415Wired4715RB154476RHB154715
UD0 through UD15, not shown, are 16 corresponding logical data bus bits from the micro-controller. FD0 through FD15 are 16 corresponding logical data bus bits from the FLASH memory controller. UD and FD data bus are wired through.
AD0 through AD7 are 8 corresponding logical data bus bits from 8-bit FLASH chip A 308a. AHD0 through AHD15 are 16 corresponding logical data bus bits from 16-bit FLASH chip A308a. BD0 through BD7 are 8 corresponding logical data bus bits from 8-bit FLASH chip B 308b. BHD0 through BHD15 are 16 corresponding logical data bus bits from 16-bit FLASH chip B 308b. 
“Wired” means no resistor network required. The connection is wired directly. Resistor networks RA 310a and RHA 310b are exclusive. Resistor network RA 310a is installed when an 8-bit FLASH chip is in use. Resistor network RHA 310b is installed when a 16-bit FLASH is in use. Resistor networks RB 312a and RHB 312b are exclusive. Resistor network RB 312a is installed when an 8-bit FLASH chip is in use. Resistor network RHB 312b is installed when a 16-bit FLASH is in use.
In order to be able to support both types of FLASH memory chips, it is required that both logic circuitries be combined together. Resistor networks RA 310a and RHA 310b are exclusive pairs serving as selector to select either 8-bit or 16-bit FLASH memory chips at physical location A 308a. Resistor networks RB 312a and RHB 312b are exclusive pairs serving as selector to select either 8-bit or 16-bit FLASH memory chips at physical location B 308b. There are a total of 96 signal traces in this circuit 300 that create great routing complexity in PCB layout. The mapping implementation is shown in Table 2. The corresponding logic equations are shown in Listing 1.
Listing 1
Logic equations of the mapping: (* is logical AND operator. + is logical OR operator)FD0=(RA0*AHD9+RHA0*AHD0)+RHB0*BHD0FD1=(RA1*AHD2+RHA1*AHD1)+RHB1*BHD1FD2=(RA2*AHD10+RHA2*AHD2)+RHB2*BHD2FD3=AHD3+RHB3*BHD3FD4=(RA4*AHD12+RHA4*AHD4)+RHB4*BHD4FD5=AHD5+RHB5*BHD5FD6=(RA6*AHD13+RHA6*AHD6)+RHB6*BHD6FD7=(RA7*AHD6+RHA7*AHD7)+RHB7*BHD7FD8=AHD8+(RB8*BHD9+RHB8*BHD8)FD9=RHA9*AHD9+(RB9*BHD2+RHB9*BHD9)FD10=RHA10*AHD10+BHD10FD11=AHD11+(RB11*BHD3+RHB11*BHD11)FD12=RHA12*AHD12+BHD12FD13=RHA13*AHD13+(RB13*BHD5+RHB13*BHD13)FD14=AHD14+(RB14*BHD13+RHB14*BHD14)FD15=AHD15+(RB15*BHD6+RHB15*BHD15)
As is shown in FIG. 4, there are 48 signal traces on both sides of resistor network RA, RHA, RB and RHB. A total of 96 traces are required to connect between FLASH memory controller and flash memory chips. Routing complexity makes it almost impossible to consider laying out support of both 8-bit and 16-bit FLASH memory chips with 16-bit FLASH memory controller.
Furthermore, different FLASH technology may have different FLASH memory data bus assignment due to package efficiency consideration. It is desirable to have a FLASH memory controller with flexible and field configurable architecture to accommodate present and future FLASH memory variations.
As FLASH memory technology becomes more mature, demand for higher performance becomes more imminent. One natural approach to improve the performance is to increase data bus bandwidth either on the FLASH memory controller side or on the FLASH memory side. It is no wonder that FLASH memory controller will expand its data bus bandwidth from 8-bit and 16-bit to 32-bit and beyond in the near future. FLASH memory chip may as well take the same expansion route for wider bandwidth. As the bandwidth increases, conventional way of adding more resistor networks to support all sizes of FLASH memory chips becomes more cumbersome.
It is desirable to provide a FLASH memory controller system to accommodate the following objectives:
Supporting 8-bit and 16-bit FLASH memory chips on the same PCB
Supporting all four FLASH memory access modes
Supporting all possible FLASH memory configurations
Improving layout routing complexity on PCB
Auto-detection and configuration of FLASH memory controller data bus
Able to scale up the controller data bus bandwidth for higher performance
The present invention addresses such a need.